XOR Gate

entity xorgate is
  port(
    in1, in2 : in bit;
    out1: out bit
  );
end entity xorgate;

architecture rtl of xorgate is
  signal var1:bit;
begin
  var1 <= in1 or in2;
  out1 <= var1 and (not in1 or not in2);
end architecture rtl;

entity xorgate_tb is
end entity;

architecture rtl of xorgate_tb is
    component xorgate port (
        in1, in2: in bit;
        out1: out bit
    );
    end component xorgate;
    for xor_0: xorgate use entity work.xorgate;
    signal in1,in2: bit;
begin
    xor_0 : xorgate port map (
        in1 => in1,
        in2 => in2
    );
    process
    type pattern_type is record
        in1,in2:bit;
    end record;
    type pattern_array is array (natural range <> ) of pattern_type;
    constant pattern : pattern_array :=
    (
    ('0','0'),
    ('0','1'),
    ('1','0'),
    ('1','1')
    );
    begin
        for i in pattern'range loop
            in1<= pattern(i).in1;
            in2<= pattern(i).in2;
            wait for 1 ns;
        end loop;
        assert false report "selesai" severity note;
        wait;
    end process;
end architecture rtl;