OR Gate

ENTITY orgates IS
PORT (
    in1, in2 : IN BIT;
    out1 : OUT BIT
);
END ENTITY orgates;

ARCHITECTURE rtl OF orgates IS
BEGIN
    out1 <= in1 OR in2;
END ARCHITECTURE rtl;

ENTITY orgates_tb IS
END ENTITY orgates_tb;

ARCHITECTURE rtl OF orgates_tb IS
    COMPONENT orgates PORT (
        in1, in2 : IN BIT;
        out1 : OUT BIT
        );
    END COMPONENT;
    FOR or_0 : orgates USE ENTITY work.orgates;
    SIGNAL in1, in2, out1 : BIT;
BEGIN
    or_0 : orgates PORT MAP(
        in1 => in1,
        in2 => in2,
        out1 => out1
    );

    PROCESS
        TYPE pattern_type IS RECORD
            in1, in2: BIT;
        END RECORD;
        TYPE pattern_array IS ARRAY (NATURAL RANGE <>) OF pattern_type;
        CONSTANT pattern : pattern_array :=
        (
        ('0', '0'),
        ('0', '1'),
        ('1', '0'),
        ('1', '1')
        );
    BEGIN
        FOR i IN pattern'RANGE LOOP
            in1 <= pattern(i).in1;
            in2 <= pattern(i).in2;
            WAIT FOR 1 ns;
        END LOOP;
        ASSERT false REPORT "Selesai." SEVERITY note;
        WAIT;
    END PROCESS;
END ARCHITECTURE rtl;