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Not Gate

Intro

Not gate atau dikenal juga sebagai inverting umumnya terdiri dari 1 input dan 1 output dimana output akan bernilai kebalikan dari input

Table kebenaran

in1 out
0 1
1 0

Task

Buat code untuk Not gate dan juga testbench nya.

The Code

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ENTITY notgate IS
PORT (
    in1 : IN BIT;
    out1 : OUT BIT
);
END ENTITY notgate;

ARCHITECTURE rtl OF notgate IS
BEGIN
    out1 <= NOT in1;
END ARCHITECTURE rtl;

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entity notgate_tb is
end entity notgate_tb;

architecture rtl of notgate_tb is
  component notgate port (
      in1: in bit;
      out1: out bit
    );
  end component notgate;
  for not_0 : notgate use entity work.notgate;
  signal in1, out1 : bit;
begin
  not_0: notgate port map (
      in1 => in1,
      out1 =>  out1);

  process
  begin
    in1 <= '0';
    wait for 1 ns;
    in1 <= '1';
    wait for 1 ns;
    assert false report "selesai" severity note;
    wait;
  end process;
end architecture rtl;
Last update: February 23, 2021

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