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NOR Gate

Intro

Tabel kebenaran

in1 in2 out1
0 0 1
0 1 1
1 0 1
1 1 0

Task

The Code

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entity norgate is
    port (
    in1, in2: in bit;
    out1 : out bit
         );
end entity norgate;

architecture rtl of norgate is
    signal tmp1: bit;
begin
    tmp1 <= in1 or in2;
    out1 <= not tmp1;
end architecture rtl;
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entity norgate_tb is
end entity norgate_tb;

architecture rtl of norgate_tb is
  -- forward declaration
  component norgate port (
      in1, in2 : in bit;
      out1 : out bit
    );
  end component;
  -- binding new component
  for nor_0: norgate use entity work.norgate;
  -- declare local variable
  signal in1,in2,out1 : bit;

begin
  nor_0 : norgate port map (
      in1 => in1,
      in2 => in2,
      out1 => out1
      );
  process
    type pattern_type is record
      in1, in2: bit;
    end record;
    type pattern_array is array (natural range <> ) of pattern_type;
    constant pattern : pattern_array :=
      (
      ('0','0'),
      ('0','1'),
      ('1','0'),
      ('1','1')
      );
  begin
    for i in pattern'range loop
      in1<= pattern(i).in1;
      in2<= pattern(i).in2;
      wait for 1 ns;
    end loop;
    assert false report "selesai" severity note;
    wait;
  end process;
end architecture rtl;

Last update: February 23, 2021

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