Skip to content

NAND Gate

Intro

Table kebenaran

in1 in2 out1
0 0 1
0 1 1
1 0 1
1 1 0

Task

The Code

 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
entity nandgate is
    port (
    in1, in2 : in bit;
    out1: out bit
    );
end entity nandgate;

architecture rtl of nandgate is
begin
    -- out1 <= (not in1 and not in2);
    out1 <= in1 nand in2;
end architecture rtl;
 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
entity nandgate_tb is
end entity nandgate_tb;

architecture rtl of nandgate_tb is
    component nandgate port (
        in1, in2: in bit;
        out1 : out bit
    );
    end component;
    for nand_0 : nandgate use entity work.nandgate;
    signal in1,in2,out1 : bit;
begin
    nand_0: nandgate port map (
        in1 => in1,
        in2 => in2,
        out1 => out1
    );
    process
    type pattern_type is record
        in1, in2 : bit;
    end record;
    type pattern_array is array (natural range <>) of pattern_type;
    constant pattern : pattern_array :=
    (
    ('0','0'),
    ('0','1'),
    ('1','0'),
    ('1','1')
    );
    begin
        for i in pattern'range loop
            in1 <= pattern(i).in1;
            in2 <= pattern(i).in2;
            wait for 1 ns;
        end loop;
        assert false report "Selesai" severity note;
        wait;
    end process;
end architecture rtl;

Last update: February 23, 2021

Comments