SR Flip-Flop

ENTITY ffsr IS
    PORT (
        S, R : IN BIT;
        Q, QBar : OUT BIT
    );
END ENTITY ffsr;

ARCHITECTURE behavioral OF ffsr IS
    SIGNAL tmp1, tmp2 : BIT;
BEGIN
    Q <= tmp1;
    tmp1 <= R NOR tmp2;
    tmp2 <= S NOR tmp1;
    QBar <= tmp2;
END ARCHITECTURE;

ENTITY ffsr_tb IS
END ENTITY ffsr_tb;

ARCHITECTURE rtl OF ffsr_tb IS
    COMPONENT ffsr PORT (
        S, R : IN BIT;
        Q, QBar : OUT BIT
        );
    END COMPONENT;
    FOR sr_0 : ffsr USE ENTITY work.ffsr;
    SIGNAL S, R, Q, QBar : BIT;
BEGIN
    sr_0 : ffsr PORT MAP(
        S => S,
        R => R
    );
    PROCESS
        TYPE partern_type IS RECORD
            S, R : BIT;
        END RECORD;
        TYPE partern_array IS ARRAY (NATURAL RANGE <>) OF partern_type;

        -- ingat SR tidak di desain untuk bisa menerima input S=1, R=1 jadi user yang harus
        -- memastikan kondisi tsb tidak pernah terjadi.
        -- juga untuk simulasi kondisi awal tidak boleh S=0, R=0 (latch/memory) klo di kondisi
        -- nyata harusnya outputnya Z tapi di simulasi langsung error.
        CONSTANT partern : partern_array :=
        (
        ('0', '1'),
        ('1', '0'),
        ('0', '0'), -- memory
        ('0', '1')
        );
    BEGIN
        FOR i IN partern'RANGE LOOP
            S <= partern(i).S;
            R <= partern(i).R;
            WAIT FOR 1 ns;
        END LOOP;
        ASSERT false REPORT "Selesai" SEVERITY note;
        WAIT;
    END PROCESS;
END ARCHITECTURE;