D Flip Flop Gate

ENTITY ffdgate IS
    PORT (
        d, clk : IN BIT;
        Q, QBar : OUT BIT
    );
END ENTITY;

ARCHITECTURE rtl Of ffdgate IS
    SIGNAL Q1, QBar1 : BIT;
BEGIN
    Q <= Q1;
    Q1 <= QBar1 NOR (D NAND clk);
    QBar1 <= Q1 NOR (NOT D NAND clk);
    QBar <= QBar1;
END ARCHITECTURE rtl;

ENTITY ffdgate_tb IS
END ENTITY;

ARCHITECTURE rtl OF ffdgate_tb IS
    COMPONENT ffdgate PORT (
        D, clk : IN BIT;
        Q, QBar : OUT BIT
        );
    END COMPONENT;
    FOR D_0 : ffdgate USE ENTITY work.ffdgate;
    SIGNAL D, clk, Q, QBar : BIT;
BEGIN
    D_0 : ffdgate PORT MAP(
        D => D,
        clk => clk
    );

    PROCESS
        TYPE pattern_type IS RECORD
            D, clk : BIT;
        END RECORD;
        TYPE pattern_array IS ARRAY (NATURAL RANGE <>) OF pattern_type;
        CONSTANT pattern : pattern_array := (
            ('0', '0'),
            ('0', '1'),
            ('1', '0'),
            ('1', '1'),
            ('0', '0'),
            ('0', '1'),
            ('1', '0'),
            ('1', '1')
        );
    BEGIN
        FOR i IN pattern'RANGE LOOP
            D <= pattern(i).D;
            clk <= pattern(i).clk;
            WAIT FOR 1 ns;
        END LOOP;
        ASSERT FALSE REPORT "Selesai" SEVERITY note;
        WAIT;
    END PROCESS;
END ARCHITECTURE rtl;